The present invention relates to a semiconductor integrated circuit including an I.sup.2 CBUS interface.
An I.sup.2 CBUS interface is constructed of two bus lines including a serial data line (hereinafter referred to as an SDA) and a serial clock line (hereinafter referred to as an SCL), and is a bus standard having the objective of effectively conducting control between ICs mutually.
Since data transmission/reception in both directions is performed by only tow bus lines, in a system initialization state inside the IC such as that immediately after power is supplied to the IC, in the case of the IC having a function as a slave device, it is essential that an SDA terminal is in a data receiving state.
A signal from an I.sup.2 BUS I/O terminal is input or output by an input/output control circuit used in the I.sup.2 CBUS interface, and two circuit examples generally used for the input/output control circuit are shown in FIG. 2 and FIG. 3.
In the prior art, as a means of realizing an input/output control circuit for determining the above-described data receiving state, a D type flip/flop circuit having a reset input as shown in FIG. 2 (hereinafter, referred to as a D-F/F circuit) with a reset input signal R from an outer reset terminal 20, or a D-F/F circuit having a reset input as shown in FIG. 3 with a reset input from a POWER.cndot.ON.cndot.CLEAR circuit (hereinafter, referred to as a POC circuit 21) which outputs one pulse immediately after power is supplied with a set pule width decided by an RC time constant, was used.
The former is controllable in the data receiving state because an externally-supplied reset signal can be input when performing system initialization such as by the supply of power.
The latter determines the data receiving state by using the output signal in the system initialization state such as by the supply of power, because the basic operation principle of the POC circuit is that of voltage detection of the power by the RC time constant.
As an advantage of an I.sup.2 CBUS interface, a simple circuit structure in which the number of pins is lessened is used. For this reason, to lessen the number of the pins, there are many cases in which a reset input terminal is not provided to a device (an IC or the like) mounted on a product, or if provided, the reset input terminal is not used according to the product specification.
Also, since a POC circuit utilizes an RC time constant, there arise problems in that it takes too much time for starting up upon the application of power, and a reset signal con not be normally generated in the case of voltage fluctuations in which the voltage does not completely fall down to a GND level (for example, an instant power failure, or the like).
Therefore, there has been desired a counter measure, which is an IC built-in circuit, that can detect that if it is in a system initialization state such as a supply of power, even in a state where the start up of power takes an extremely long time and in a state where voltage fluctuations do not completely fall down in voltage to the GND level, and is capable of controlling in the data receiving state.